1. Technical Field
The present invention relates generally to dynamic logic circuits, and more particularly to a dynamic circuit and operating method for reducing power consumption by controlling leakage current.
2. Description of the Related Art
Dynamic logic circuits are an attractive alternative to static logic circuits, as the number of transistors required to implement a given logic function is typically reduced, particularly when providing complex logical implementations as are be found in processor functional blocks such as arithmetic units and other blocks requiring outputs derived from a large number of inputs.
As the operating voltage of dynamic circuits is decreased, an increasing portion of the power consumption of such circuits is now determined by leakage in and through the output stages of the individual logic circuits. A large portion of the leakage is generated at the inputs of the output inverters of each dynamic gate. Leakage occurs from the internal evaluation node of the dynamic circuit through the gate of the transistor in the output stage that is coupled to the power-supply rail opposite the value of the evaluation node. The largest portion of that leakage is associated with the precharge state of the evaluation node and therefore is mostly associated with the particular inverter transistor that conducts when the gate is in the precharge state. For example, if the precharge value is the high (positive) voltage logic state, the typical N-channel device used to drive the logic low state in the typical output inverter is conducting. Gate tunneling causes some leakage current to occur through the N-channel device to the low voltage power supply rail.
While it is possible to supply foot devices throughout the dynamic circuit for power control, doing so disables all of the outputs of the individual gates, causing the dynamic circuit to be in a non-functional power-saving mode. Typically, this is accomplished by turning off the dynamic logic clock to completely disable the dynamic circuit. As such, only a very “coarse” control of leakage power consumption can be achieved, as outputs feeding a next logic stage are invalidated and if the evaluation node is also isolated by a disabled footer, the state held at that node is likewise invalidated.
Therefore, it would be desirable to provide a dynamic circuit architecture such that a finer interval may be used to enter and exit power-savings mode so that power consumption due to leakage can be reduced. It would further be desirable to provide a control mechanism such that the standby mode can be controlled on-the fly, without causing a loss of state information or invalid logic combinations at subsequent stage inputs.